This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to reducing the amount of surface area on a die required for an integrated circuit.
The sizes of the various components and structures that are formed during an integrated circuit fabrication process are continually being reduced. This reduction in the size of the various elements of the integrated circuit tends to result in a general reduction in the overall size of the integrated circuit. For example, an integrated circuit with one million transistors can fit within the surface area of a much smaller die than it could have just a few years ago. Alternately, within a given die size, a greater number of transistors and other structures can now be fabricated than was previously possible.
However, such advances in reducing the size of the elements of an integrated circuit have not come without a myriad of new challenges. For example, one such challenge has been to provide a sufficient number of electrical contacts for the connections between the integrated circuit and the package substrate or other structure to which it is electrically connected. As the number of transistors within the integrated circuit has increased, so too has the required number of bonding pads on the integrated circuit increased. The space required by this explosion in the number of bonding pads has somewhat offset the gains that have been won in reducing the space required for the active circuitry.
Several methods have been devised to reduce the total amount of space required for the greater number of bonding pads. For example, instead of having bonding pads located just at the peripheral portions of the die, bonding pads have been moved to interior portions of the integrated circuit, which is then mounted with solder bumps as a flip chip. However, it is preferable in some applications to have wire bonded integrated circuits rather than bump mounted flip chip integrated circuits. Another method has been to provide multiple concentric rings or rows of bonding pads around the peripheral edge of the die, rather than just the single ring that was sufficient for a smaller number of transistors. However, the surface area on the die required for the electrically conductive connections between the outer rings of bonding pads tends to reduce the amount of space available for the inner rings of bonding pads, thus offsetting some of the gains that are realized by having multiple rings of bonding pads.
One way to somewhat alleviate this condition is to reduce the width of the bonding pads on the inner rings, which allows more space on the surface of the integrated circuit for the electrical connections to the bonding pads in the outer rings. However, reducing the width of a bonding pad makes it more difficult to bond to. Thus, there is a practical limit, dictated at least in part by the state of the art of wire bonding equipment and wire bonding techniques, as to how narrow a bonding pad can be made. This practical limit puts a cap on the gains that can be realized by reducing the width of the bonding pad to reduce the total amount of space required by the bonding pads.
What is needed, therefore, is an integrated circuit design that provides an increased number of bonding pads at the peripheral edge of the integrated circuit.
The above and other needs are met by an integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Electrically conductive outer bonding pads are disposed in an outer ring adjacent the peripheral edge of the substrate. The outer bonding pads are formed within the top most electrically conductive layer, and have a first width. Electrically conductive inner bonding pads are disposed in an inner ring interior to and concentric with the outer ring of bonding pads. The inner bonding pads are formed within the top most electrically conductive layer, and have a second width.
Electrically conductive inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying electrically conductive layer, and have a third width that is less than the second width of the inner bonding pads, thereby defining a gap having a fourth width between the inner connectors. Electrically conductive outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying electrically conductive layer, and have a fifth width that is less than the fourth width of the gap between the inner connectors.
By placing the inner and outer connectors of the bonding pads on an underlying electrically conductive layer in this manner, the connectors can be narrower than the bonding pads. This enables the bonding pads to be left at a width that is easily sufficient for good wire bonding. However, the connectors, being narrower than the bonding pads, have sufficient room between them for the routing of other connectors. Specifically, the narrower connectors for the inner row of bonding pads have sufficient space between them for the routing of the connectors for the outer row of bonding pads. Thus, the bonding pads of the inner row can be placed directly adjacent one another, and no space is lost between them for routing of the outer connectors. Thus, there is more space for larger bonding pads.
In various embodiments, adjacent ones of the inner bonding pads are disposed at a pitch that is narrower than the fifth width of the outer connectors. Preferably, the first width of the outer bonding pads is equal to the second width of the inner bonding pads. Adjacent ones of the outer bonding pads are disposed at a first pitch and adjacent ones of the inner bonding pads are disposed at a second pitch and the first pitch is preferably equal to the second pitch. Preferably, the underlying electrically conductive layer is a first electrically conductive layer below the top most electrically conductive layer. The outer ring of bonding pads and the inner ring of bonding pads preferably include all bonding pads of the integrated circuit. Preferably, the inner ring of bonding pads is disposed over the circuitry of the integrated circuit. The outer ring of bonding pads may also be disposed over the circuitry of the integrated circuit. In one embodiment the inner connectors comprise vias to the circuitry. Also described is a packaged integrated circuit including the integrated circuit as described above.
According to another aspect of the invention there is described an integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included is a top most electrically conductive layer and an underlying electrically conductive layer. Electrically conductive outer bonding pads are disposed in an outer ring adjacent the peripheral edge of the substrate. The outer bonding pads are formed within the top most electrically conductive layer, and have a first width. Electrically conductive inner bonding pads are disposed in an inner ring interior to and concentric with the outer ring of bonding pads. The inner bonding pads are formed within the top most electrically conductive layer, have a second width, and are disposed over the circuitry of the integrated circuit.
Electrically conductive inner connectors electrically connect the inner bonding pads to the circuitry without routing between the outer bonding pads. The inner connectors are formed within the underlying electrically conductive layer. Electrically conductive outer connectors electrically connect the outer bonding pads to the circuitry without routing between the inner bonding pads. The outer connectors are formed within the underlying electrically conductive layer.
With the inner bonding pads so disposed over the circuitry, it is unnecessary for either the inner connectors or the outer connectors to route by one another. In this manner, there is sufficient space for the inner bonding pads to be placed directly adjacent one another, and also for the outer bonding pads to be placed directly adjacent one another. Thus, less total space is used for the bonding pads, and the bonding pads can be formed at a size that is sufficient for good wire bonding.
In various embodiments, the first width of the outer bonding pads is equal to the second width of the inner bonding pads. Adjacent ones of the outer bonding pads are disposed at a first pitch and adjacent ones of the inner bonding pads are disposed at a second pitch and the first pitch is preferably equal to the second pitch. In one embodiment the inner connectors comprise vias to the circuitry. Also described is a packaged integrated circuit including the integrated circuit described above.
According to yet another aspect of the invention there is described an integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included is a top most electrically conductive layer and an underlying electrically conductive layer. Electrically conductive outer bonding pads are disposed in an outer ring adjacent the peripheral edge of the substrate. The outer bonding pads are formed within the top most electrically conductive layer, and have a first width. The outer bonding pads are disposed over the circuitry of the integrated circuit. Electrically conductive inner bonding pads are disposed in an inner ring interior to and concentric with the outer ring of bonding pads. The inner bonding pads are formed within the top most electrically conductive layer, and have a second width. The inner bonding pads are disposed over the circuitry of the integrated circuit.
Electrically conductive outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying electrically conductive layer, and have a fifth width that is less than the first width of the outer bonding pads, thereby defining a gap having a fourth width between the outer connectors. Electrically conductive inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying electrically conductive layer, and have a third width that is less than the fifth width of the gap between the outer connectors.
This embodiment is similar to the first embodiment described above, except that both the inner ring and the outer ring of bonding pads are disposed over the circuitry, and the narrower outer connectors provide sufficient space for the inner connectors to route between them to connect to the circuitry. Thus, the bonding pads of the outer row can be placed directly adjacent one another, and no space is lost between them for routing of the inner connectors. Thus, there is more space for larger bonding pads.
In various embodiments, adjacent ones of the outer bonding pads are disposed at a pitch that is narrower than the third width of the inner connectors. The first width of the outer bonding pads is preferably equal to the second width of the inner bonding pads. Adjacent ones of the outer bonding pads are disposed at a first pitch and adjacent ones of the inner bonding pads are disposed at a second pitch and the first pitch is preferably equal to the second pitch. Also described is a packaged integrated circuit including the integrated circuit as described above.